Semiconductor device

ABSTRACT

A semiconductor device includes a diode and a semiconductor substrate. The diode includes a p-type anode region and an n-type cathode region. A lifetime control layer is provided in an area within the cathode region. The area is located on a back side than a middle portion of the semiconductor substrate in a thickness direction of the semiconductor substrate. The lifetime control layer has crystal defects which are distributed along a planar direction of the semiconductor substrate. A peak value of a crystal defect density in the lifetime control layer is higher than a crystal defect density of a front side region adjacent to the lifetime control layer on a front side of the lifetime control layer and a crystal defect density of a back side region adjacent to the lifetime control layer on a back side of the lifetime control layer.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority to Japanese Patent Application No. 2015-042227 filed on Mar. 4, 2015, the entire contents of which are hereby incorporated by reference into the present application.

TECHNICAL FIELD

The technique disclosed herein relates to a semiconductor device.

DESCRIPTION OF RELATED ART

Japanese Patent Application Publication No. 2013-48230 discloses a diode. Hereinbelow, Japanese Patent Application Publication No. 2013-48230 will be termed Patent Reference 1. This diode includes an anode electrode, a p-type anode region that makes contact with the anode electrode, and an n-type cathode region provided on a back side of the anode region. Further, this diode includes an n-type pillar region. The pillar region penetrates the anode region from a front surface of a semiconductor substrate and reaches a cathode region. An upper end of the pillar region is connected to an anode region. In this diode, the anode electrode and the cathode region are connected by the pillar region. When a forward voltage to be applied to this diode is raised, a current flows in the cathode region from the anode electrode through the pillar region. Since primary carriers in this current are electrons, hardly any hole flows into the cathode region even if this current flows. Further, since the cathode region is connected to the anode electrode via the pillar region, a potential difference is less likely to occur in a pn junction at an interface of the anode region and the cathode region despite the forward voltage application on the diode. Due to this, this pn junction does not turn on at this stage. When the forward voltage is further raised, the pn junction at the interface of the anode region and the cathode region turns on. Due to this, holes flow in from the anode region to the cathode region. As above, in this diode, the pn junction at the interface of the anode region and the cathode region is less prone to being turned on upon raising the forward voltage of the diode, by which the flow of holes to the cathode region is suppressed. When the voltage applied to the diode is switched from the forward voltage to a reverse voltage, the diode performs a reverse recovery operation. That is, the holes in the cathode region are discharged to the anode electrode, and a reverse recovery current flows in the diode. In this diode, since the holes flowing into the cathode region upon the application of the forward voltage on the diode are scarce, the holes discharged from the cathode region to the anode electrode upon when the diode performs the reverse recovery operation are also in small number. Due to this, the reverse recovery current is less likely to flow in this diode.

BRIEF SUMMARY OF INVENTION

In the aforementioned diode provided with the pillar region, a further improvement in a reverse recovery characteristic (that is, suppression on the flow of reverse recovery current) is desired.

A technique that improves the reverse recovery characteristic of a diode by providing a lifetime control layer with a high crystal defect density in a cathode region of the diode is known. Since carrier lifetime is short in the lifetime control layer, holes can be extinguished within a short period of time. Accordingly, by providing the lifetime control layer in the cathode region, the holes can be extinguished in the cathode region upon a reverse recovery operation, and a reverse recovery characteristic can thereby be improved. In a general diode (diode not provided with a pillar region), a hole density in the cathode region in a vicinity of an anode region becomes high when the diode is on. Due to this, in the general diode, the lifetime control layer is provided in the cathode region in the vicinity of the anode region. Based on this knowledge, the inventors of the present application had considered to further improve the reverse recovery characteristic by providing the lifetime control layer in the diode provided with the pillar region. However, it has been found that in the diode provided with the pillar region, the reverse recovery characteristic is not so much improved even when the lifetime control layer is provided in the cathode region in the vicinity of the anode region similar to the conventional configuration. As a result of having studied the cause thereof, the followings were confirmed. In the diode provided with the pillar region, inflow of holes to the cathode region from the anode region is suppressed by the pillar region. Due to this, it has been found that when the diode is on, unlike the conventional diode, the cathode region in the vicinity of the anode region comes to have a low hole density, whereas the hole density becomes high in the cathode region on a farther side from the anode region. Due to this, the reverse recovery characteristic cannot so much be improved even if the lifetime control layer is provided in the cathode region in the vicinity of the anode region.

In the present disclosure, a semiconductor device that comprises a diode provided with a pillar region, with a satisfactory reverse recovery characteristic is provided. The semiconductor device comprises and a semiconductor substrate. The diode comprises an anode electrode, a cathode electrode, an anode region, a barrier region, a pillar region, and a cathode region. The anode electrode is provided on a front surface of the semiconductor substrate. The cathode electrode is provided on a back surface of the semiconductor substrate. The anode region is provided in the semiconductor substrate, and is a p-type region connected to the anode electrode. The barrier region is provided in the semiconductor substrate, and is an n-type region in contact with the anode region from a back side of the anode region. The pillar region is provided in the semiconductor substrate, and is an n-type region connected to the anode electrode. The pillar region pierces through the anode region from the front surface of the semiconductor substrate and reaches the barrier region. The cathode region is provided in the semiconductor substrate, and is an n-type region disposed on a back side of the barrier region and connected to the cathode electrode. A lifetime control layer is provided in an area within the cathode region, the area being located on a back side than a middle portion of the semiconductor substrate in a thickness direction of the semiconductor substrate. The lifetime control layer has crystal defects which are distributed along a planar direction of the semiconductor substrate. A peak value of a crystal defect density in the lifetime control layer is higher than a crystal defect density of a front side region adjacent to the lifetime control layer on a front side of the lifetime control layer and a crystal defect density of a back side region adjacent to the lifetime control layer on a back side of the lifetime control layer.

Notably, the barrier region and the cathode region may be separated by a p-type region, or may be connected. In a case where the barrier region and the cathode region are connected, these regions may configure one n-type region in which these regions are substantially integrated. Further, the planar direction means a direction vertically intersecting the thickness direction of the semiconductor substrate (direction that is parallel to the front surface or the back surface of the semiconductor substrate).

The diode of this semiconductor device comprises the pillar region. Further, the lifetime control layer is provided in the area within the cathode region that is located on the back side than the middle portion of the semiconductor substrate in the thickness direction of the semiconductor substrate (that is, a range on a farther side from the anode region). That is, the lifetime control layer is provided in the area where the hole density is to become high when diode having the pillar region turns on. Accordingly, when the diode performs a reverse recovery operation, a large number of holes can be extinguished by the lifetime control layer. Due to this, a reverse recovery current is less likely to flow in this diode. According to this technique, the reverse recovery characteristic of the diode provided with the pillar region can further be improved.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows a vertical cross sectional view of a semiconductor device 10.

FIG. 2 is a graph showing a crystal defect density distribution in a thickness direction of a semiconductor substrate 12.

FIG. 3 is a graph showing a hole density distribution in a cathode region 38 when a diode is on.

FIG. 4 is a graph showing a relationship of a position of a lifetime control layer 50, and a forward voltage effect Vf and a reverse recovery loss Err of the diode.

FIG. 5 shows a vertical cross sectional view of a semiconductor device of a variant.

DETAILED DESCRIPTION OF INVENTION

A semiconductor device 10 of an embodiment shown in FIG. 1 comprises a semiconductor substrate 12, electrodes provided respectively on a front surface 12 a and a back surface 12 b of the semiconductor substrate 12, insulators, and the like. A thickness of the semiconductor substrate 12 is about 120 μm. The semiconductor substrate 12 comprises an IGBT region 16 in which an IGBT is provided, and a diode region 18 in which a diode is provided. That is, the semiconductor device 10 is a so-called RC-IGBT.

The semiconductor substrate 12 is configured of silicon. A plurality of trenches 40 is provided on the front surface 12 a of the semiconductor substrate 12. Each trench 40 extends parallel to each other in a vertical direction relative to a sheet surface of FIG. 1.

An inner surface of each trench 40 in the IGBT region 16 is covered by a gate insulating film 42. A gate electrode 44 is arranged inside each trench 40 in the IGBT region 16. The gate electrodes 44 are insulated from the semiconductor substrate 12 by the gate insulating films 42. A front surface of each gate electrode 44 is covered by an interlayer insulating film 46.

An inner surface of each trench 40 in the diode region 18 is covered by an insulating film 52. A control electrode 54 is arranged inside each trench 40 in the diode region 18. The control electrodes 54 are insulated from the semiconductor substrate 12 by the insulating films 52. A front surface of each control electrode 54 is covered by an interlayer insulating film 56. Potential of the control electrodes 54 is controlled independent from potential of the gate electrodes 44.

An upper electrode 60 is provided on the front surface 12 a of the semiconductor substrate 12. The upper electrode 60 is insulated from the gate electrodes 44 by the interlayer insulating films 46, and is insulated from the control electrodes 54 by the interlayer insulating films 56. A lower electrode 62 is provided on the back surface 12 b of the semiconductor substrate 12.

Emitter regions 20, a front-side body region 22, an IGBT barrier region 23, IGBT pillar regions 24, a back-side body region 25, a drift region 26, and a collector region 32 are provided in the IGBT region 16.

The emitter regions 20 are n-type regions, and are exposed on the front surface 12 a of the semiconductor substrate 12. The emitter regions 20 make ohmic contact with the upper electrode 60. The emitter regions 20 make contact with the gate insulating films 42.

The front-side body region 22 is provided to surround the emitter regions 20, and makes contact with the emitter regions 20. Further, the front-side body region 22 makes contact with the gate insulating films 42 under the emitter regions 20. That is, each of the gate electrodes 44 faces the front-side body region 22 positioned under the corresponding emitter region 20 via the corresponding gate insulating film 42. The front-side body region 22 comprises body contact regions 22 a and a low-concentration body region 22 b.

The body contact regions 22 a are p-type regions containing p-type impurities at a high concentration. The body contact regions 22 a are exposed on the front surface 12 a of the semiconductor substrate 12. The body contact regions 22 a make ohmic contact with the upper electrode 60. Each of the body contact regions 22 a is adjacent to the corresponding emitter region 20.

The low-concentration body region 22 b is a p-type region with a lower p-type impurity concentration than that of the body contact regions 22 a. The low-concentration body region 22 b is provided under the emitter regions 20 and the body contact regions 22 a. The low-concentration body region 22 b makes contact with the gate insulating films 42 under the emitter regions 20. Further, parts of the low-concentration body region 22 b are exposed on the front surface 12 a of the semiconductor substrate 12 at positions adjacent to the body contact regions 22 a.

The IGBT barrier region 23 is an n-type region, and is provided under the front-side body region 22 (that is, the low-concentration body region 22 b). A pn junction 49 is provided at an interface between the IGBT barrier region 23 and the front-side body region 22. The IGBT barrier region 23 is separated from the emitter regions 20 by the front-side body region 22. The IGBT barrier region 23 makes contact with the gate insulating films 42 under the front-side body region 22.

The IGBT pillar regions 24 are provided in each area interposed between the trenches 40 in the IGBT region 16. The IGBT pillar regions 24 are n-type regions, and are adjacent to the front-side body region 22. The IGBT pillar regions 24 extend long in a thickness direction of the semiconductor substrate 12 from the front surface 12 a of the semiconductor substrate 12. The IGBT pillar regions 24 pierce through the front-side body region 22 and reach the IGBT barrier region 23. A lower end of each of the IGBT pillar regions 24 is connected to the IGBT barrier region 23. An upper end of each of the IGBT pillar regions 24 makes Schottky contact with the upper electrode 60. That is, a Schottky junction 48 is provided between each of the IGBT pillar regions 24 and the upper electrode 60.

The back-side body region 25 is a p-type region, and is provided under the IGBT barrier region 23. The back-side body region 25 is separated from the front-side body region 22 by the IGBT barrier region 23. The back-side body region 25 makes contact with the gate insulating films 42 under the IGBT barrier region 23. That is, the gate electrodes 44 face the back-side body region 25 via the gate insulating films 42.

The drift region 26 is an n-type region, and is provided under the back-side body region 25. The drift region 26 is separated from the IGBT barrier region 23 by the back-side body region 25. The drift region 26 comprises a low-concentration drift region 26 a and a buffer region 26 b.

The low-concentration drift region 26 a is an n-type region that contains n-type impurities at a lower concentration than the emitter regions 20 and the buffer region 26 b. The low-concentration drift region 26 a is provided under the back-side body region 25. The low-concentration drift region 26 a is separated from the IGBT barrier region 23 by the back-side body region 25. Under the back-side body region 25, the low-concentration drift region 26 a makes contact with the gate insulating films 42 in vicinities of the lower ends of the trenches 40.

The buffer region 26 b is an n-type region that contains n-type impurities at a higher concentration than the low-concentration drift region 26 a. The buffer region 26 b is provided under the low-concentration drift region 26 a.

The collector region 32 is a p-type region that contains p-type impurities at a high concentration. The collector region 32 is provided under the drift region 26 (that is, the buffer region 26 b). The collector region 32 is separated from the back-side body region 25 by the drift region 26. The collector region 32 is exposed on the back surface 12 b of the semiconductor substrate 12, The collector region 32 makes ohmic contact with the lower electrode 62.

IGBT connected between the upper electrode 60 and the lower electrode 62 is configured in the IGBT region 16 by the emitter regions 20, the front-side body region 22, the IGBT barrier region 23, the IGBT pillar regions 24, the back-side body region 25, the drift region 26, the collector region 32, the gate electrodes 44, and the like. In a case where the semiconductor device 10 operates as the IGBT, the upper electrode 60 is an emitter electrode, and the lower electrode 62 is a collector electrode.

A front-side anode region 34, a diode barrier region 35, diode pillar regions 36, a back-side anode region 37, and a cathode region 38 are provided in the diode region 18.

The front-side anode region 34 is a p-type region, and is exposed on the front surface 12 a of the semiconductor substrate 12. Further, the front-side anode region 34 makes contact with the insulating films 52. The front-side anode region 34 comprises anode contact regions 34 a and a low-concentration anode region 34 b.

The anode contact regions 34 a are p-type regions containing p-type impurities at a high concentration. The anode contact regions 34 a are exposed on the front surface 12 a of the semiconductor substrate 12. The anode contact regions 34 a make ohmic contact with the upper electrode 60.

The low-concentration anode region 34 b, is a p-type region with a lower p-type impurity concentration than the anode contact regions 34 a. The low-concentration anode region 34 b is formed in an area surrounding the anode contact regions 34 a, including areas under each of the anode contact regions 34 a. The low-concentration anode region 34 b makes contact with the insulating films 52. Further, parts of the low-concentration anode realm 34 b are exposed on the front surface 12 a of the semiconductor substrate 12 at positions adjacent to the anode contact regions 34 a.

The diode barrier region 35 is an n-type region, and is provided under the front-side anode region 34 (that is the low-concentration anode region 34 b). A pn junction 59 is provided at an interface between the diode harrier region 35 and the front-side anode region 34. The diode barrier region 35 makes contact with the insulating films 52 under the front-side anode region 34. The diode barrier region 35 is formed at substantially a same depth as the IGBT barrier region 23.

The diode pillar regions 36 are provided in each area interposed between the trenches 40 in the diode region 18. The diode pillar regions 36 are n-type regions, and are adjacent to the front-side anode region 34. The diode pillar regions 36 extend long in a thickness direction of the semiconductor substrate 12 from the front surface 12 a of the semiconductor substrate 12. The diode pillar regions 36 pierce through the front-side anode region 34 and reach the diode barrier region 35. A lower end of each of the diode pillar regions 36 is connected to the diode barrier region 35. An upper end of each of the diode pillar regions 36 makes Schottky contact with the upper electrode 60. That is a Schottky junction 58 is provided between each of the diode pillar regions 36 and the upper electrode 60.

The back-side anode region 37 is a p-type region, and is provided under the diode barrier region 35. A p-type impurity concentration of the back-side anode region 37 is lower than a p-type impurity concentration of the low-concentration anode region 34 b. The back-side anode region 37 is separated from the front-side anode region 34 by the diode barrier region 35. The back-side anode region 37 makes contact with the insulating films 52 under the diode barrier region 35. The back-side anode region 37 is formed at substantially a same depth as the back-side body region 25 in the IGBT region 16.

The cathode region 38 is an n-type region connected to the drift region 26. The cathode region 38 is provided under the back-side anode region 37. The cathode region 38 is separated from the diode barrier region 35 by the back-side anode region 37. The cathode region 38 is exposed on the back surface 12 b of the semiconductor substrate 12. The cathode region 38 makes ohmic contact with the lower electrode 62. The cathode region 38 comprises a low-concentration drift region 38 a, a buffer region 38 b, and a cathode contact region 38 c.

The low-concentration drift region 38 a is provided under the back-side anode region 37. The low-concentration drift region 38 a is separated from the diode barrier region 35 by the back-side anode region 37. Under the back-side anode region 37, the low-concentration drift region 38 a makes contact with the insulating films 52 in vicinities of the lower ends of the trenches 40. The low-concentration drift region 38 a has an n-type impurity concentration that is substantially a same as the low-concentration drift region 26 a in the IGBT region 16. The low-concentration drift region 38 a is connected to the low-concentration drift region 26 a of the IGBT region 16.

The buffer region 38 b is provided under the low-concentration drift region 38 a. The buffer region 38 b is an n-type region that contains n-type impurities at a higher concentration than the low-concentration drift region 38 a. The buffer region 38 b has substantially a same n-type impurity concentration as the buffer region 26 b of the IGBT region 16. The buffer region 38 b is connected to the buffer region 26 b of the IGBT region 16.

The cathode contact region 38 c is an n-type region that contains n-type impurities at a higher concentration than the buffer region 38 b. The cathode contact region 38 c is provided under the buffer region 38 b. The cathode contact region 38 c is exposed on the back surface 12 b of the semiconductor substrate 12. The cathode contact region 38 c makes ohmic contact with the lower electrode 62. The cathode contact region 38 c is adjacent to the collector region 32 in the IGBT region 16.

A diode connected between the upper electrode 60 and the lower electrode 62 is configured in the diode region 18 by the front-side anode region 34, the diode harrier region 35, the diode pillar regions 36, the back-side anode region 37, the cathode region 38, and the like. Notably, since the p-type impurity concentration of the back-side anode region 37 is low, carriers pass through the back-side anode region 37 upon when this diode turns on. That is, the pn junction 59 at the interface between the front-side anode region 34 and the diode barrier region 35 function as a substantial pn diode, and the back-side anode region 37 functions as a current passage. In a case where the semiconductor device 10 operates as the diode, the upper electrode 60 is an anode electrode, and the lower electrode 62 is a cathode electrode. That is the diode is connected in reverse parallel relative to the IGBT.

The lifetime control layer 50 with a high crystal defect density is provided in the low-concentration drift region 26 a and the low-concentration drift region 38 a. The lifetime control layer 50 is distributed in a layer-like shape along a planar direction of the semiconductor substrate 12, across the low-concentration drift region 26 a and the low-concentration drift region 38 a. The lifetime control layer 50 is provided in an area that is on a back surface 12 b side than a middle portion C1 of the semiconductor substrate 12 in the thickness direction. More specifically, the lifetime control layer 50 is provided in vicinities of the buffer regions 26 b, 38 b.

FIG. 2 shows a crystal defect density distribution in the thickness direction of the semiconductor substrate 12. Notably, the crystal defect density is distributed in a similar way as shown in FIG. 2 in both of the IGBT region 16 and the diode region 18. As shown in FIG. 2, the crystal defect density in the lifetime control layer 50 is higher than a crystal defect density Nb in a semiconductor layer 83 that is located on a front surface 12 a side than the lifetime control layer 50 and a crystal defect density Na in a semiconductor layer 84 that is located on a back surface 12 b side than the lifetime control layer 50. That is, a peak value of the crystal defect density in the lifetime control layer 50 is higher than each of the crystal defect densities Na, Nb. A crystal defect density peak is formed in the lifetime control layer 50. Further, the crystal defect density Nb of the semiconductor layer 83 is higher than the crystal defect density Na of the semiconductor layer 84. The crystal defect density distribution shown in FIG. 2 can be achieved by implanting charged particles (for example, helium ions) to the semiconductor substrate 12 from the front surface 12 a side in a manufacturing process of the semiconductor device 10. The charged particles are implanted so that they stop at a depth corresponding to the lifetime control layer 50. When the charged particles stop within the semiconductor substrate 12, crystal defects are formed at a high density in a vicinity of the stopped position. Due to this, the lifetime control layer 50 with the high crystal defect density is thereby formed in the vicinity of the stopped position. Further, though at a lower density than that of the lifetime control layer 50, crystal defects are formed also in an area in the semiconductor substrate 12 where the charged particles pass through (that is, the semiconductor layer 83 on the front surface 12 a side than the lifetime control layer 50). Accordingly, the crystal defect density Nb the semiconductor layer 83 on the front surface 12 a side than the lifetime control layer 50 becomes higher than the crystal defect density Na of the semiconductor layer 84 on the back surface 12 b side than the lifetime control layer 50. Since the lifetime control layer 50 is formed in the vicinities of the buffer regions 26 b, 38 b, the crystal defects are distributed at the density Nb in majorities of the low-concentration drift regions 26 a, 38 a.

Next, an operation of the diode in the diode region 18 will be described. A case will be considered in which a forward voltage (that is, voltage with which the upper electrode 60 becomes positive relative to the lower electrode 62) to be applied to the diode is gradually raised. When the forward voltage exceeds a startup voltage of the Schottky junction 58, the Schottky junction 58 turns on. Then, as shown by a solid arrow 70 in FIG. 1, a current (which is hereafter referred to as current 70) flows. That is, electrons flow in an opposite direction in a passage shown by the solid arrow 70. More specifically, the electrons flow from the lower electrode 62 to the upper electrode 60 through the cathode region 38, the backside anode region 37, the diode bather region 35, and the diode pillar regions 36. Since the current 70 is generated by the flow of electrons, hardly any hole flows into the cathode region 38 despite the flow of the current 70. Further, the pn junction 59 is configured in the diode region 18 by the front-side anode region 34 and the diode barrier region 35. The voltage applied to the pn junction 59 is substantially equal to a voltage applied between the upper electrode 60 and the diode barrier region 35. Since a start-up voltage of the pn junction 59 is higher than the start-up voltage of the Schottky junction 58, the pn junction 59 does not turn on at this stage.

When the forward voltage is further raised, the current 70 increases. Since the diode pillar regions 36 have resistances, the increase in the current 70 causes the voltage between the diode barrier region 35 and the upper electrode 60 to rise. When this voltage rises to the start-up voltage of the pn junction 59, the pn junction 59 turns on. Due to this, as shown by a broken arrow 72 in FIG. 1, a current (which is hereafter referred to as current 72) flows. That is, holes flow from the upper electrode 60 to the lower electrode 62 through the front-side anode region 34, the diode barrier region 35, the back-side anode region 37, and the cathode region 38 along the broken arrow 72. Further, the electrons flow in an opposite direction in a passage shown by the broken arrow 72. When the current 72 flows, the holes flow into the cathode region 38 from the front-side anode region 34.

As above, in this diode, a timing when the pit junction 59 turns on is delayed by the current 70 flowing in the diode pillar regions 36. Due to this, the holes are suppressed from flowing into the cathode region 38. FIG. 3 shows a hole density distribution in the cathode region 38 when the diode (that is, the pn junction 59) is on. Notably, a horizontal axis in FIG. 3 shows the depth from the front surface 12 a of the semiconductor substrate 12 (that is, a distance measured from the front surface 12 a of the semiconductor substrate 12 downward). As shown in FIG. 3, the diode provided with the pillar regions 36 have higher hole density on the back surface 12 b side within the cathode region 38.

Thereafter, when the voltage to be applied to the diode is switched to a reverse voltage, the diode performs the reverse recovery operation. That is, the holes present in the cathode region 38 are discharged to the upper electrode 60. Due to this, the reverse recovery current flows in the diode. As described above, since the holes are suppressed from flowing into the cathode region 38 when the diode is on, the holes discharged from the cathode region 38 to the upper electrode 60 upon the reverse recovery operation of the diode are scarce. Due to this, the reverse recovery current is less likely to flow in this diode.

Further, the lifetime control layer 50 having the high crystal defect density is provided in the low-concentration drift region 38 a. The crystal defects function as recombination centers of the carriers. Due to this, in the lifetime control layer 50, carrier lifetime is short. Accordingly, when the diode performs the reverse recovery operation, the holes in the cathode region 38 extinguish by the recombination taking place in the lifetime control layer 50. Due to this, the holes discharged from the cathode region 38 to the upper electrode 60 upon the reverse recovery operation become scarce. Especially, the lifetime control layer 50 is provided in the low-concentration drift region 38 a in the area that is on the back surface 12 b side than the middle portion C1 in the thickness direction of the semiconductor substrate 12. That is, the lifetime control layer 50 is provided in the area within the low-concentration drift region 38 a where the holes would be present at high density when the diode is on. Due to this, a large number of holes can be extinguished upon the reverse recovery operation by the recombination. Due to this, the reverse recovery current can be reduced more effectively.

FIG. 4 shows a relationship between the position of the lifetime control layer 50 in the thickness direction of the semiconductor substrate 12, and a forward voltage drop Vf and a reverse recovery loss Err (that is, loss generated upon the reverse recovery operation) in the diode. In FIG. 4, a distance L measured downward from the front surface 12 a of the semiconductor substrate 12 (that is, the depth) is shown as the position of the lifetime control layer 50. In FIG. 4, cases where the distance L is 40 μm, 60 μm, 70 μm, 80 μm, 90 μm, and 100 μm are shown. No matter which of the above value is assumed by the distance L, the lifetime control layer 50 is positioned in the low-concentration drift region 38 a. As described above, since the thickness of the semiconductor substrate 12 is 120 μm, the lifetime control layer 50 is positioned on the front surface 12 a side than the middle portion C1 in the thickness direction of the semiconductor substrate 12 when the distance L is 40 μm. Further, When the distance L is 60 μm, the lifetime control layer 50 is positioned at the middle portion C1 in the thickness direction of the semiconductor substrate 12. When the distance L is 70 μm, 80 μm, 90 μm, or 100 μm the lifetime control layer 50 is positioned on the back surface 12 b side than the middle portion C1 in the thickness direction of the semiconductor substrate 12. As is apparent from FIG. 4, the reverse recovery loss Err becomes smaller with longer distance L. This means that the holes extinguished in the lifetime control layer 50 upon the reverse recovery operation is greater in number with longer distance L. Further, the forward voltage drop Vf becomes larger with longer distance L. This means that the holes extinguished in the lifetime control layer 50 upon the reverse recovery operation is greater in number when the diode is on. From these results, it can be understood that the holes can more efficiently be extinguished by providing the lifetime control layer 50 at a position closer to the back surface 12 b. As is apparent from FIG. 4, the holes can more efficiently be extinguished by providing the lifetime control layer 50 on the back surface 12 b side than the middle portion C1 in the thickness direction of the semiconductor substrate 12, and the reverse recovery loss Err can thereby be reduced effectively. For example, as shown in FIG. 4, the reverse recovery loss Err can be halved or reduced even more in the eases where the distance L is 70 μm or more, as compared to the case where the distance L is 40 μm.

Further, the crystal defects are provided also at the relatively high density Nb in the low-concentration drift region 38 a on the front surface 12 a side than the lifetime control layer 50. Due to this, the holes can be extinguished by recombination upon the reverse recovery operation, even in the low-concentration drift region 38 a on the upper side than the lifetime control layer 50. Due to this as well, the reverse recovery current can be reduced.

As described above, in the semiconductor device 10, the reverse recovery characteristic of the diode is improved by the diode pillar regions 36. Further, in the semiconductor device 10, the reverse recovery characteristic of the diode is improved also by the crystal defects in the cathode region 38. Especially, in the diode provided with the diode pillar regions 36, the reverse recovery characteristic of the diode can efficiently be improved by providing the lifetime control layer 50 in the area on the back surface 12 b side than the middle portion C1 in the thickness direction of the semiconductor substrate 12.

Further, when the reverse voltage is applied to the diode, a depletion layer extends from the back-side anode region 37 into the low-concentration drift region 38 a. With the low-concentration drift region 38 a being depleted, the diode comes to be in a non-conducting state. In the semiconductor device 10, since the lifetime control layer 50 is provided at a position far away from the back-side anode region 37, a leak current is less likely to flow when the low-concentration drift region 38 a is depleted. Further, as described above, as compared to the case where the lifetime control layer 50 is provided on the front surface 12 a side (for example, when the distance L is 40 μm), the reverse recovery loss Err can effectively be reduced in the case of providing the lifetime control layer 50 on the back surface 12 b side. Due to this, in the case of providing the lifetime control layer 50 on the back surface 12 b side, the reverse recovery loss Err can be reduced sufficiently even if the crystal defect density of the lifetime control layer 50 is made low compared to the case of providing the lifetime control layer 50 on the front surface 12 a side. As above, in the case of making the crystal defect density of the lifetime control layer 50 positioned on the back surface 12 b side lower, the leak current that may be generated upon when the low-concentration drift region 38 a is depleted can further be suppressed. Further, in this case, a charged particle irradiating step for forming the lifetime control layer 50 can be completed within a short period of time, and a manufacturing efficiency of the semiconductor device 10 can be improved.

Notably, a parasitic diode is formed within the IGBT region 16 by the pn junction 49. Further, the IGBT barrier region 23 on the lower side of the pn junction 49 is connected to the upper electrode 60 through the IGBT pillar regions 24. Accordingly, when the forward voltage (that is, the potential of the upper electrode 60) rises as described above, the current generated by the electrons flows first in the IGBT pillar regions 24. Thereafter, when the forward voltage further increases, the pn junction 49 configuring the parasitic diode turns on. As above, the timing when the pa junction 49 turns on is delayed in the IGBT region 16 similarly and the holes are suppressed from flowing into the low-concentration drift regions 26 a, 38 a from the front-side body region 22. Due to this, the reverse recovery current is suppressed.

Next, an operation of the diode in the IGBT will be described. When a potential equal to or higher than a threshold (that is, emitter-gate voltage) is applied to the gate electrodes 44, channels are formed in the low-concentration body region 22 b and the back-side body region 25 in areas adjacent to the gate insulating films 42. In a state where a potential by which the lower electrode 62 comes to be at a higher potential than the upper electrode 60 is being applied and when the channels are formed, the electrons flow from the upper electrode 60 to the lower electrode 62 through the channels in the emitter regions 20, the channels in the front-side body region 22, the IGBT bather region 23, the channels in the back-side body region 25, the drift region 26, and the collector region 32. Further, the holes flow from the lower electrode 62 to the upper electrode 60 through the collector region 32, the drift region 26, the back-side body region 25, the IGBT barrier region 23, and the front-side body region 22. That is, the IGBT turns on.

Thereafter, when the potential of the gate electrodes 44 is lowered, the channels disappear and the IGBT turns off. Then, the holes that had been present in the drift region 26 when the IGBT was on are discharged to the upper electrode 60 through the front-side body region 22. Due to this, a tail current flows in the IGBT upon the turnoff. When the tail current is large, a turnoff loss of the IGBT becomes large. However, in this IGBT, the lifetime control layer 50 is formed in the low-concentration drift region 26 a. Accordingly, the holes in the drift region 26 are extinguished by recombination in the lifetime control layer 50 upon the turnoff of the IGBT. Accordingly, the tail current is small in this IGBT. In the IGBT, the holes can efficiently be extinguished with the crystal defects formed at a position within the drift region 26 close to the back surface 12 b, such as the lifetime control layer 50. Accordingly, by using the lifetime control layer 50, the holes can efficiently be extinguished, and the tail current can further be reduced. Due to this, the turnoff loss generated in this IGBT is small.

As described above, according to the semiconductor device 10, the reverse recovery loss of the diode and the turnoff loss of the IGBT can both be reduced. In both of the diode region 18 and the IGBT region 16, the losses can efficiently be reduced by forming the lifetime control layer 50 in positions within the cathode region 38 and the drift region 26 closer to the back surface 12 b. Due to this, the lifetime control layer 50 can be formed at the substantially same depth in the diode region 18 and the IGBT region 16. Due to this, in the manufacturing process of the semiconductor device 10, the lifetime control layer 50 can be formed at a same time in the diode region 18 and the IGBT region 16. That is, there is no need to separately form the lifetime control layer in the diode region 18 and the IGBT region 16 so that the depth thereof becomes different. Due to this, the semiconductor device 10 can efficiently be manufactured.

Notably, in the semiconductor device 10 in the above-described embodiment the p-type backside body region 25 and the back-side anode region 37 are respectively provided between the barrier regions 23, 35 and the low-concentration drift regions 26 a, 38 a. However, as shown in FIG. 5, the back-side body region 25 and the back-side anode region 37 may not be provided. That is, the IGBT barrier region 23 may be in contact with the low-concentration drift region 26 a, and these regions may be configured by a substantially one n-type region in which these regions are connected to each other. Further, the diode barrier region 35 may be in contact with the low-concentration drift region 38 a, and these regions may be configured by a substantially one n-type region in which these regions are connected to each other. Further, in the case of FIG. 5, the n-type impurity concentration in the barrier regions 23, 35 may be higher than the n-type impurity concentration in the low-concentration drift regions 26 a, 38 a. Further, the n-type impurity concentration in the barrier regions 23, 35 may be equal to the n-type impurity concentration in the low-concentration drift regions 26 a, 38 a.

Notably, in the above-described embodiment, the control electrode 54 is provided in the diode region 18, however, the control electrode 54 does not have to be provided in the diode region 18.

Further, in the semiconductor device 10 in the above-described embodiment, the anode electrode and the emitter electrode are facilitated by a common upper electrode 60. However, the anode electrode may be separated from the emitter electrode. Further, the semiconductor device 10 in the above-described embodiment comprises the lower electrode 62 in which the cathode electrode and the collector electrode are facilitated in common. However, the cathode electrode may be separated from the collector electrode.

Further, in the above-described embodiment, the pillar regions 24, 36 make Schottky contact with the upper electrode 60. However, the pillar regions 24, 36 may make ohmic contact with the upper electrode 60.

Further, in the above-described embodiment, the crystal defect density Na of the semiconductor layer 84 on the back surface 12 b side than the lifetime control layer 50 is lower than the crystal defect density Nb of the semiconductor layer 83 on the front surface 12 a side than the lifetime control layer 50. However, the crystal defect density Na in the semiconductor layer 84 may be higher than the crystal defect density Nb in the semiconductor layer 83. Such a crystal defect density distribution can be achieved by implanting the charged particles (for example, helium ions) to the semiconductor substrate 12 from the back surface 12 b side. However, in this case, the crystal defect density Nb becomes low in a wider area on the front surface 12 a side than the lifetime control layer 50, so the effect of reducing the reverse recovery current is somewhat less than the above-described embodiment.

Hereinbelow, a relationship of the constituent features of the embodiment and the constituent features of the claims will be described. The upper electrode 60 in the embodiment is an example of an anode electrode and an emitter electrode in the claims. The lower electrode 62 in the embodiment is an example of a cathode electrode and a collector electrode in the claims. The front-side anode region 34 in the embodiment is an example of an anode region in the claims. The diode barrier region 35 in the embodiment is an example of a bather region in the claims. The diode pillar regions 36 in the embodiment is an example of a pillar region in the claims. The back-side anode region 37 in the embodiment is an example of a separate region in the claims. The front-side body region 22 in the embodiment is an example of a body region in the claims.

Some technical features disclosed herein will be listed. Note that the respective technical features as below are useful even when each of them are used independently.

In one example of the semiconductor device disclosed herein, a p-type separate region separating the barrier region and the cathode region may be provided between the barrier region and the cathode region.

One example of the semiconductor device disclosed herein may higher comprise an IGBT. In this case, the IGBT comprises an emitter electrode, a collector electrode, an emitter region, a body region, an IGBT drift region, a collector region, and a gate electrode. The emitter electrode is provided on the front surface. The collector electrode is provided on the back surface. The emitter region is provided in the semiconductor substrate, and is an n-type region connected to the emitter region. The body region is provided in the semiconductor substrate and is a p-type region in contact with the emitter region from a back side of the emitter region. The IGBT drift region is provided in the semiconductor substrate, and is an n-type region disposed at a back side of the body region, connected to the cathode region, and separated from the emitter region by the body region. The collector region is provided in the semiconductor substrate, and is a p-type region in contact with the IGBT drift region from a back side of the IGBT drift region, connected to the collector electrode, and separated from the body region by the IGBT drift region. The gate electrode faces the body region via a gate insulating film in a range where the emitter region and the IGBT drift region are separated by the body region. The lifetime control layer extends across the cathode region and the IGBT drill region.

In this configuration, the semiconductor device comprises the diode and the IGBT. In this configuration, the lifetime control layer is distributed across the cathode region and the IGBT drift region. Due to this, the lifetime control layer is provided within the IGBT drift region on the back side than the middle portion of the semiconductor substrate (that is, in the IGBT drift region in the vicinity of the collector region). With the lifetime control layer provided at such a position, the switching loss of the IGBT can effectively be reduced. Further, according to this configuration, the lifetime control layer is provided at the substantially same position (depth) in both the diode region and the IGBT region. Due to this, the lifetime control layer can be formed at once in both the diode region and the IGBT region. Accordingly, the semiconductor device can efficiently be manufactured.

Specific examples of the present invention are described above in detail, but these examples are merely illustrative and place no limitation on the scope of the patent claims. The technology described in the patent claims also encompasses various changes and modifications to the specific examples described above. The technical elements explained in the present specification or drawings provide technical utility either independently or through various combinations. The present invention is not limited to the combinations described at the time the claims are filed. Further, the purpose of the examples shown by the present specification or drawings is to satisfy multiple objectives simultaneously, and satisfying any one of those objectives gives technical utility to the present invention. 

What is claimed is:
 1. A semiconductor device comprising a diode and a semiconductor substrate, wherein the diode comprises: an anode electrode provided on a front surface of the semiconductor substrate; a cathode electrode provided on a back surface of the semiconductor substrate; a p-type anode region provided in the semiconductor substrate and connected to the anode electrode; an n-type barrier region provided in the semiconductor substrate and in contact with the anode region from a back side of the anode region; an n-type pillar region provided in the semiconductor substrate and connected to the anode electrode, the pillar region piercing through the anode region from the front surface of the semiconductor substrate and reaching the barrier region; and an n-type cathode region provided in the semiconductor substrate, disposed on a back side of the barrier region, and connected to the cathode electrode, wherein a lifetime control layer is provided in an area within the cathode region, the area being located on a back side than a middle portion of the semiconductor substrate in a thickness direction of the semiconductor substrate, the lifetime control layer having crystal defects which are distributed along a planar direction of the semiconductor substrate, and a peak value of a crystal defect density in the lifetime control layer is higher than a crystal defect density of a front side region adjacent to the lifetime control layer on a front side of the lifetime control layer and a crystal defect density of a back side region adjacent to the lifetime control layer on a back side of the lifetime control layer.
 2. The semiconductor device according to claim 1, wherein a p-type separate region separating the barrier region and the cathode region is provided between the barrier region and the cathode region.
 3. The semiconductor device according to claim 1, further comprising an IGBT, wherein the IGBT comprises: an emitter electrode provided on the front surface; a collector electrode provided on the back surface; n-type emitter region provided in the semiconductor substrate and connected to the emitter region; a p-type body region provided in the semiconductor substrate and in contact with the emitter region from a back side of the emitter region; an n-type IGBT drift region provided in the semiconductor substrate, disposed at a back side of the body region, connected to the cathode electrode, and separated from the emitter region by the body region; a p-type collector region provided in the semiconductor substrate, in contact with the IGBT drift region from a back side of the IGBT drift region, connected to the collector electrode, and separated from the body region by the IGBT drift region; and a gate electrode facing the body region via a gate insulating film in a range where the emitter region and the IGBT drift region are separated by the body region, wherein the lifetime control layer extends across the cathode region and the IGBT drift region.
 4. The semiconductor device according to claim 1, further comprising an IGBT, wherein the IGBT comprises: an emitter electrode provided on the front surface; a collector electrode provided on the back surface; an n-type emitter region provided in the semiconductor substrate and connected to the emitter region; a p-type body region provided in the semiconductor substrate and in contact with the emitter region from a back side of the emitter region; an n-type IGBT drift region provided in the semiconductor substrate, disposed at a back side of the body region, connected to the cathode electrode, and separated from the emitter region by the body region; a p-type collector region provided in the semiconductor substrate, in contact with the IGBT drift region from a back side of the IGBT drift region, connected to the collector electrode, and separated from the body region by the IGBT drift region; and a gate electrode facing the body region via a gate insulating film in a range where the emitter region and the IGBT drift region are separated by the body region, wherein the lifetime control layer extends across the cathode region and the IGBT drift region. 